Error correction has been explored to secure the integrity of digital information transmitted from one device to another. Known algorithms generally apply additional parity bits to message data bits in order to provide error detection and/or correction. Parity methods are known for detecting and correcting a single error bit in parallel data transfer. However, methods for detection and correction of double or multiple-bit errors tend to increase the number of data bits required substantially.
Memory errors appear for two reasons. One reason is a fault in the transport of the data from the memory to the data user and the other reason is an error in the memory itself. If the transport suffers a fault, the errors are likely to be repetitive on a particular line in parallel data connectors. However, errors in the memory itself are likely to be non-repetitive and spread across different lines.
(Error-Correcting Codes) are designed to correct unpredictable non-repetitive errors, with each set of bits being seen as new and corrected appropriately. However, errors also occur which are repetitive errors where one line of a parallel interconnect is in error. Where data is moved over a parallel bus, there is a significant chance of repetitive errors on the same line of the bus.
Hamming codes are error-correcting codes that can detect and correct single, double, or multiple-bit errors depending on the number of parity bits used. Hamming codes are described in Hamming, R. W., “Error Detecting and Correcting Codes”, Bell System Technical Journal, 29, 147-160 (1950). Pure Rectangular or Triangular codes based on variants of the Hamming solution require large numbers of additional parity bits to encode redundancy into an interface.
JTAG (Joint Test Action Group) scanning tests printed circuit boards using a boundary scan. It provides fault detection and not correction on chip interfaces. This also requires systems to enter a specific test state to run the scan.